1. Field of the Invention
The disclosure relates in general to a three-dimensional (3D) stacked semiconductor structure and method of manufacturing the same, and more particularly to the 3D stacked semiconductor structure manufactured by self-aligned process.
2. Description of the Related Art
A nonvolatile semiconductor memory device is typically designed to securely hold data even when power is lost or removed from the memory device. Various types of nonvolatile memory devices have been proposed in the related art. Also, manufactures have been looking for new developments or techniques combination for stacking multiple planes of memory cells, so as to achieve greater storage capacity. For example, several types of multi-layer stackable NAND-type flash memory structures have been proposed. However, the typical 3D memory structure suffers from several problems.
FIG. 1A˜FIG. 1C illustrate a conventional method of manufacturing a 3D stacked semiconductor structure, for example, a 3D VG (vertical gate) NAND memory array structure. The conventional 3D stacked semiconductor structure includes several multi-layered pillars 11M formed on a substrate 10 and spaced apart from each other, and one of the multi-layered pillars 11M comprises a plurality of insulating layers (i.e. including a top insulating layer 111T, a bottom insulating layer 111B and several insulating layers 111 between the top and bottom insulating layers) and a plurality of conductive layers 121 arranged alternately. In the conventional method, the top conductor (such as polysilicon) is etched twice, i.e. poly-contact (PLC) process and poly-alignment (PLA) process. As shown in FIG. 1A, the PLC process is performed to form the patterned conductor 171 and several holes 171a, wherein the holes 171a expose the top surface of the substrate 10. As shown in FIG. 1B, the PLA process is performed by covering the structure on the substrate 10 of FIG. 1A, followed by forming the photo mask 182 for patterning the patterned conductor 171. As shown in FIG. 1C, the patterned conductor 171 of FIG. 1A is further etched to form the conductive blocks 19, wherein each conductive block 19 comprises a lower portion 19a (vertical to the substrate 10 along the y-direction) between the charging-trapping layers (vertical channels) 16 of the adjacent multi-layered pillars 11M, and an upper portion 19b connected to the lower portion 19a and extended along the x-direction as a word line.
According to the conventional method, the upper portion 19b (top PL conductor) is formed by twice etching. The PLA process of the conventional method is a not self-aligned process. Conductor-PL is remained for WL connection currently, and the PLA process has narrow process window due to non-self aligned process. Worse WL connection would be occurred due to twice etching processes (i.e. PLC process+PLA process). Non-self-aligned SSL cut is conducted to form the SSL (string select line) islands, so that the morphology of SSL islands would be worse. Also, in the conventional method, the upper portion 19b and the lower portion 19a of each conductive block 19 are made from the same material, which can not satisfy the different requirements of the WLs (i.e. the upper portion 19b) and the gate material (i.e. the lower portion 19a, the conductor between the charging-trapping layers 16).